1. Field of the Invention
The present invention generally relates to semiconductor devices and more particularly to formation of MOSFETs capable of sustaining voltages greater than three volts within a high-performance SOI CMOS technology.
2. Background Description
Silicon on insulator n-MOSFETs, designed for low-voltage, high-performance CMOS circuits, have significant limitations in drain-to-source breakdown voltage (VBDs) due to floating body effects. Because the body of a MOSFET in SOI has no explicit electrical connection available to the circuit designer and hence xe2x80x98floatsxe2x80x99, the voltage present on this body will be a function of the use conditions on the gate, source and drain terminals prior to the next use, and is variable and difficult to predict. This leads to (effectively) unpredictable behavior of an SOI MOSFET. In particular, drain avalanche currents forward-bias the body with respect to the source leading to NPN bipolar gain. This results in exponential growth of current from drain to source, thereby limiting the maximum voltage sustainable.
It is therefore an object of the present invention to provide a silicon-on-insulator device which is able to withstand higher operating voltages than those conventionally attainable.
The extension ion implantations (typically consisting of a shallow n+ high-dose implant, a low-dose higher energy boron halo implant and third implant to induce damage to the silicon lattice at the junction edge, such as germanium or indium) which are implanted into both the source and drains of a conventional MOSFET, are, in this invention, selectively excluded from the drain side of the inventive high-voltage MOSFET by suitable design of the block mask (designated as BH) which is used during these implants. This results in the high values of leakage from the body to the source, but not the drain. The n+ extension implant is responsible for good electrical conductivity between the MOSFET channel (when the device is on) to the deep source and/or drain (n+ or p+ for n-type MOSFETs or p-type MOSFETs, respectively) where contacts are made to interconnects. These deeper junction regions are formed some distance away from the gate to avoid disadvantageous short-channel effects.
A new block mask (designated as SC) is added. This mask provides openings only over the drains of high-voltage MOSFETs, through which a Lightly-Doped Drain (LDD) ion implantation (e.g. Phosphorus at 5xc3x971013 cmxe2x88x922) is performed, possibly in combination with a light halo (e.g. boron at 1xc3x971013 cmxe2x88x922 at 35 keV) to control short-channel effects. The LDD is a region of the drain diffusion where the doping is preferably on the order of 1017-1018 cmxe2x88x923 (n-type for nfets, p-type for pfets). This region is immediately adjacent to the channel and below the gate electrode. A phosphorous ion-implantation of dose ≈1-5xc3x9710xe2x88x9213 cmxe2x88x922 after gate electrode formation (etch) can be used to form this LDD. The LDD lowers the electric fields at the drain and thus lowers the avalanche current substantially. No damage implant is included in this SC opening to keep drain-to-body leakage low.
The invention provides significantly increased drain-to-source breakdown voltage, VBDS, by decreasing avalanche currents at the drain both by removal of the standard damaging source implants and by introducing a field-lowering LDD implant at the drain. MOSFETs, and particularly, n-type MOSFETs, are limited in the maximum voltage that may safely be applied from drain to source, Vds-max, by a mechanism known as avalanche breakdown. As Vds is increased, a very high electric field forms in the channel beneath the gate immediately adjacent to the drain junctions. This high field causes a fraction of channel (inversion layer) electrons to create electron-hole pairs in this regions which results in an electric current from the body to the drain (avalanche current). This current draws the body voltage more positive, which in turn, lowers the MOSFET Vt and results in greater channel current which, in turn, results in more avalanche current. At some critical voltage, VBDS, this process will run away resulting in damage to the MOSFET or other circuit elements connected to it. Thus, Vds-max is less than VBDS and is directly related to the magnitude of the avalanche currents generated nearby the drain of the MOSFET as well as the ability of the damaged region adjacent to the source to conduct charge to the source from the body.